The invention is related to serial-to-parallel converters and more particularly to a converter in which the input data bits are sequentially supplied via a direct data path to output storage means and released in parallel therefrom. The length of a serial input word or parallel output word may be changed while the bit positions of the parallel output word remain unchanged with respect to the sequence in which the serial data bits are received.
Digital data processing systems frequently include circuits operating at different clock frequencies, thus requiring converters from high to low or low to high speed of data transfer between these circuits. One such known device is a serial-to-parallel converter which receives serial input data sequentially at a relatively high clock frequency, for example, from a peripheral device, such as a magnetic recording and playback device and it provides parallel output data at a significantly lower clock frequency, as it may be necessary for further processing, for example by a digital computer.
One type of prior art serial-to-parallel converter utilizes input shift registers into which the serial input data is fed sequentially and clocked therethrough in serial form. The serial data from the register is sequentially applied to parallel output latches and released in parallel in response to a parallel clock signal. Such prior art system is described and shown for example in a manual entitled HBR-3000 Magnetic Recorder, Provisional Data, No. 001050, Section 3, Serial-to-Parallel, and Schematic Drawing No. 1255592-01, issued Feb. 1, 1978 by Ampex Corporation, assignee of the present patent application.
It is a significant disadvantage of the above type of prior art converters that at each serial clock pulse the input data is shifted by one bit position through the device. Consequently, it is difficult to trace the individual data bits during operation and the bit positions are not known until the data appears on the output latches just prior to being clocked out in form of a parallel word. Consequently, data retrieval and trouble shooting are obstructed. Also, there is no serial word synchronizing pulse provided in these prior art devices. If the length of the serial input word or parallel output word is changed, the first and subsequent data bits appear at different output terminals for each such change. The foregoing also occurs after operation has been interrupted and restarted. These prior art converters are not suitable for applications where it is necessary to maintain known data bit positions during operation.
Other types of known prior art serial-to-parallel converters have a synchronizing data code supplied sequentially with the incoming data and through the same data path, via an input register. These converters require additional circuits for detecting the time when the synchronizing data is contained in the input register. Besides, in these prior art converters, the length of the serial or parallel word cannot be readily changed.